1. Field
The present disclosure generally relates to substrates for electronic devices, including substrates for use in integrated circuit packages.
2. Background Art
Integrated circuit (IC) devices can include an IC die that is included in an IC package. The IC die can be formed out of silicon and can have circuits formed therein. The IC package can include an IC package substrate to which the IC die is mounted. One configuration for mounting an IC die to an IC package substrate is a flip-chip configuration in which the active surface of the IC die faces the IC package substrate. In this configuration, conductive elements of the IC die can be used to couple the IC die to conductive pads on the IC package substrate. For example, the conductive elements can include solder bumps that be attached to pads of the IC package substrate using a reflow process. In a solder reflow process, the IC die can be pressed against the IC package substrate and heated in a reflow oven such that the solder melts. After the solder cools, connections are formed between the IC die's conductive elements and the IC package substrate's pads. The IC package substrate can further include pads on the opposite surface as the IC die, which can be used to couple the IC device to a printed circuit board (PCB), e.g., through pins or solder balls.
In one implementation, the IC die can have conductive elements formed along the periphery of its active surface. In this implementation, the IC package substrate can include pads formed in a bond on lead (BoL) configuration. When the pads are in a BoL configuration, connections from the IC die are routed to other locations on the IC package substrate using traces arranged in a “fan out” pattern or a “fan in” pattern. A BoL configuration may not be suitable for an IC die that includes connection elements throughout its active surface in a matrix configuration, because the interior traces would intersect with other traces. In another configuration, the IC package substrate includes a matrix of pads, each of which is coupled to another layer of the IC package substrate through, e.g., a via. Conventional substrates that include a matrix of pads, however, can be expensive to manufacture because they require an expensive solder on pad (SOP) process to couple the conductive elements to the IC package substrate's pads.
The present disclosure will now be described with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number identifies the drawing in which the reference number first appears.